module key_FSM(
	clk,
	rst_n,
	key_flag,
	key_state,

	times
);

	input clk;
	input rst_n;
	input key_flag;
	input key_state;
	
	output reg [2:0]times;

	
	wire pedge;
	wire nedge;
	
	assign pedge = key_flag && key_state;
	assign nedge = key_flag && !key_state;
	
	reg [2:0]state;
	reg [29:0]cnt;
	
	always@(posedge clk or negedge rst_n)
	if(!rst_n)
		begin
			state <= 0;	
			times <= 3'b0;
		end 
	else 
		begin
			case(state)
				0: if(nedge)
					begin
						state <= 1;
						times <= 3'h0;
					end
					else
						begin
							state <= 0;
							times <= times;
						end
						
				1: if(nedge)
					begin
						state <= 2;
						times <= 3'h1;
					end
					else
						begin
							state <= 1;
							times <= times;
						end
					
				2: if(nedge)
					begin
						state <= 3;
						times <= 3'h2;
					end
					else
						begin
							state <= 2;
							times <= times;
						end
						
				3: if(nedge)
					begin
						state <= 4;
						times <= 3'h3;
					end
					else
						begin
							state <= 3;
							times <= times;
						end
					
				4: if(nedge)
					begin
						state <= 0;
						times <= 3'h4;
					end
					else
						begin
							state <= 4;
							times <= times;
						end
					default:;
				endcase
			end
													
endmodule 